This invention relates to transistors, and more particularly to partially isolated fin-shaped field effect transistors (FinFET) and methods for their construction. In particular, the channel portion of the fins is on buried silicon oxide, while the source and/or drain portions of the fins land on silicon.
For 14 nm node, FinFET technology is considered as one of the front-up options. In a conventional FinFET integration process, the fins are typically first patterned, and followed with gate patterning and spacer etching. However, fin erosion is a key concern in the gate and spacer etching processes. While increasing the thickness of fin hard mask is helpful to minimize the fin erosion, it is not friendly for trigate channel FinFET integration. In addition, Fin epitaxial merge is challenging from epitaxial thin film growth point of view. The epitaxial silicon might be formed between fin gaps but with some fins not epitaxially merged while others are. This can impact the finFET device performance significantly. Moreover, if the fin epitaxial process is not well controlled, it may cause source and drain short problem at the gate line ends.